A FPGA-based compute node for the PANDA
نویسندگان
چکیده
The new proton antiproton annihilation experiment at Darmstadt, PANDA, foresees to run with a frequency of up to 10 interactions per second and will deliver an expected data rate of several tens of gigabytes per second. In this scenario, real time processing, for intelligent data compression and event selection, is mandatory. A general purpose compute node based on eld programmable gate arrays (FPGA) is being designed at the University of Gieÿen. Each compute node will be equipped with ve Virtex-4 FX FPGAs, multiple gigabit Ethernet ports, four optical links and 13 RocketIO ports connected to the ATCA full mesh backplane. Each node will be realized as a full size ATCA board. The full mesh backplane of the ATCA shelf and the multiple gigabit ports provide the bandwidth necessary to transport the large amount of data delivered by the detectors.
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